Higher level hardware synthesis

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In the mid-1960s, Gordon Moore noted that integrated circuits were doubling in complexity annually, predicting this trend would last for a decade. Despite initial skepticism regarding his "unrealistic optimism," Moore's prediction has proven accurate for much longer than anticipated, with modern chips containing millions of transistors. This exponential growth in transistor density has driven the computer revolution but also introduced significant design challenges for engineers and computer scientists. To leverage the vast number of available transistors, new complexity management techniques are essential. This monograph explores the design of high-level languages for hardware description and the methods for translating these languages into silicon. We introduce SAFL, a first-order functional language tailored for behavioral hardware description, and detail the implementation of its silicon compiler. The high-level features of SAFL enable the use of program analyses and optimizations not found in current synthesis systems. Additionally, SAFL abstracts low-level implementation details, allowing it to be compiled into various design styles, including fully synchronous and globally asynchronous locally synchronous (GALS) circuits.