Mapping of a Machine Learning Algorithm Representation to Distributed Disaggregated FPGAs

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The winding down of Moore’s law and the end of Dennard scaling have increased the demand for specialized accelerators, such as field-programmable gate arrays (FPGAs), in cloud and high-performance computing to support demanding workloads like machine learning and artificial intelligence. However, despite their performance and energy-efficiency advantages, FPGAs are not widely deployed due to challenging tool support. This thesis aims to promote broader FPGA adoption through improvements on three levels. First, it presents a system architecture for efficiently managing a large number of disaggregated network-attached FPGAs. By utilizing partial reconfiguration, the architecture separates non-privileged user logic from privileged system logic, creating heterogeneous clusters of traditional CPU servers and FPGA nodes connected via the same network, for which no established programming model exists. Second, it revisits programming models for these clusters, arguing that the Message Passing Interface (MPI) is suitable for programming CPU-FPGA clusters. Finally, it develops a framework for mapping deep neural network (DNN) models to distributed disaggregated FPGAs. This includes a meta-compiler, called DOSA, which evaluates, selects, and combines existing DNN-to-FPGA tools, leveraging previous research to generate more efficient solutions.