VLSI CHIP DESIGN USING HIGH SPEED ATM SWITCH

The High Performance (HiPer) Switch Architecture offers a detailed engineering approach modeled in C++ and VHDL, showcasing advanced traffic management for ATM networks. It achieves a remarkably low Cell Loss Ratio of 1.0x 10-8 with a 64-cell buffer under a high-traffic scenario. The design, implemented in a 0.5 m CMOS VLSI process, demonstrates a peak throughput of 200 Mbps per output port. The architecture effectively manages diverse applications such as voice, video, and data, emphasizing traffic and congestion control strategies to meet specified quality of service (QoS) requirements.